The present invention relates to FPGAs (field programmable gate arrays).
FIG. 12 shows a general configuration of an FPGA. In the figure, the circuit blocks 810 and 811 each including logic circuits are arranged. These circuit blocks 810 and 811 are connectable to each other through interconnection 831. Further, these circuit blocks 810 and 811 are also connectable to external terminals (which are not shown in this figure) through the interconnection 831, respectively. In addition, connecting means 821 are arranged between the interconnection 831 and each of the circuit blocks 810 and 811, respectively. Each of these connecting means 821 are programmed/not programmed from a turned-on state to a turned-off state or vice versa in accordance with a program prepared by a user after the FPGA has been shipped. In other words, it is possible to obtain an apparatus providing with desired functions by connecting the interconnection 831 and the circuit blocks 810 and 811 freely in accordance with the programmed connecting means 821.
FIG. 13 shows another FPGA in which a plurality of circuit blocks 910 and 911 is arranged in the first row ROW 1 and circuit blocks 920 and 921 in the second row ROW 2, respectively. Further, interconnection 951 is provided to programmably connect the circuit blocks 910, 911, 920 and 921 each other or to programmably connect the circuit blocks 910 to 921 with external terminals, respectively. Programmable connecting means 941 are arranged between the circuit blocks 910 to 921 and the interconnection 951, respectively and further other connecting means 931 are arranged on interconnection 951, respectively. Using the FPGA, it is possible to obtain desired functions by programming the connecting means 931 and 941, respectively.
In the above-mentioned FPGAs, however, there exists a problem as follows: since users would use any part of the prepared circuit blocks, connecting means and interconnection, all the interconnections and all the connecting means must be perfect or non-defective. In other words, if any one of a plurality of the circuit blocks will not function or only one of a plurality of interconnections is disconnected or any one of a plurality of the connecting means cannot be programmed, the desired functions could not be obtained. Recently, the capacity of FPGAs has been increasing, and it causes a low production yield and a high chip cost of FPGAs.